
double-link:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005f0 <_init>:
  4005f0:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005f4:	910003fd 	mov	x29, sp
  4005f8:	94000048 	bl	400718 <call_weak_fn>
  4005fc:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400600:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400610 <.plt>:
  400610:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400614:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10084>
  400618:	f947fe11 	ldr	x17, [x16, #4088]
  40061c:	913fe210 	add	x16, x16, #0xff8
  400620:	d61f0220 	br	x17
  400624:	d503201f 	nop
  400628:	d503201f 	nop
  40062c:	d503201f 	nop

0000000000400630 <exit@plt>:
  400630:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400634:	f9400211 	ldr	x17, [x16]
  400638:	91000210 	add	x16, x16, #0x0
  40063c:	d61f0220 	br	x17

0000000000400640 <malloc@plt>:
  400640:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400644:	f9400611 	ldr	x17, [x16, #8]
  400648:	91002210 	add	x16, x16, #0x8
  40064c:	d61f0220 	br	x17

0000000000400650 <__libc_start_main@plt>:
  400650:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400654:	f9400a11 	ldr	x17, [x16, #16]
  400658:	91004210 	add	x16, x16, #0x10
  40065c:	d61f0220 	br	x17

0000000000400660 <__gmon_start__@plt>:
  400660:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400664:	f9400e11 	ldr	x17, [x16, #24]
  400668:	91006210 	add	x16, x16, #0x18
  40066c:	d61f0220 	br	x17

0000000000400670 <abort@plt>:
  400670:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400674:	f9401211 	ldr	x17, [x16, #32]
  400678:	91008210 	add	x16, x16, #0x20
  40067c:	d61f0220 	br	x17

0000000000400680 <puts@plt>:
  400680:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400684:	f9401611 	ldr	x17, [x16, #40]
  400688:	9100a210 	add	x16, x16, #0x28
  40068c:	d61f0220 	br	x17

0000000000400690 <free@plt>:
  400690:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400694:	f9401a11 	ldr	x17, [x16, #48]
  400698:	9100c210 	add	x16, x16, #0x30
  40069c:	d61f0220 	br	x17

00000000004006a0 <__isoc99_scanf@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006a4:	f9401e11 	ldr	x17, [x16, #56]
  4006a8:	9100e210 	add	x16, x16, #0x38
  4006ac:	d61f0220 	br	x17

00000000004006b0 <printf@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006b4:	f9402211 	ldr	x17, [x16, #64]
  4006b8:	91010210 	add	x16, x16, #0x40
  4006bc:	d61f0220 	br	x17

00000000004006c0 <putchar@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4006c4:	f9402611 	ldr	x17, [x16, #72]
  4006c8:	91012210 	add	x16, x16, #0x48
  4006cc:	d61f0220 	br	x17

Disassembly of section .text:

00000000004006d0 <_start>:
  4006d0:	d280001d 	mov	x29, #0x0                   	// #0
  4006d4:	d280001e 	mov	x30, #0x0                   	// #0
  4006d8:	aa0003e5 	mov	x5, x0
  4006dc:	f94003e1 	ldr	x1, [sp]
  4006e0:	910023e2 	add	x2, sp, #0x8
  4006e4:	910003e6 	mov	x6, sp
  4006e8:	580000c0 	ldr	x0, 400700 <_start+0x30>
  4006ec:	580000e3 	ldr	x3, 400708 <_start+0x38>
  4006f0:	58000104 	ldr	x4, 400710 <_start+0x40>
  4006f4:	97ffffd7 	bl	400650 <__libc_start_main@plt>
  4006f8:	97ffffde 	bl	400670 <abort@plt>
  4006fc:	00000000 	.inst	0x00000000 ; undefined
  400700:	00400bec 	.word	0x00400bec
  400704:	00000000 	.word	0x00000000
  400708:	00400d48 	.word	0x00400d48
  40070c:	00000000 	.word	0x00000000
  400710:	00400dc8 	.word	0x00400dc8
  400714:	00000000 	.word	0x00000000

0000000000400718 <call_weak_fn>:
  400718:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10084>
  40071c:	f947f000 	ldr	x0, [x0, #4064]
  400720:	b4000040 	cbz	x0, 400728 <call_weak_fn+0x10>
  400724:	17ffffcf 	b	400660 <__gmon_start__@plt>
  400728:	d65f03c0 	ret
  40072c:	00000000 	.inst	0x00000000 ; undefined

0000000000400730 <deregister_tm_clones>:
  400730:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400734:	91018000 	add	x0, x0, #0x60
  400738:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40073c:	91018021 	add	x1, x1, #0x60
  400740:	eb00003f 	cmp	x1, x0
  400744:	540000a0 	b.eq	400758 <deregister_tm_clones+0x28>  // b.none
  400748:	90000001 	adrp	x1, 400000 <_init-0x5f0>
  40074c:	f946f421 	ldr	x1, [x1, #3560]
  400750:	b4000041 	cbz	x1, 400758 <deregister_tm_clones+0x28>
  400754:	d61f0020 	br	x1
  400758:	d65f03c0 	ret
  40075c:	d503201f 	nop

0000000000400760 <register_tm_clones>:
  400760:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400764:	91018000 	add	x0, x0, #0x60
  400768:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40076c:	91018021 	add	x1, x1, #0x60
  400770:	cb000021 	sub	x1, x1, x0
  400774:	9343fc21 	asr	x1, x1, #3
  400778:	8b41fc21 	add	x1, x1, x1, lsr #63
  40077c:	9341fc21 	asr	x1, x1, #1
  400780:	b40000a1 	cbz	x1, 400794 <register_tm_clones+0x34>
  400784:	90000002 	adrp	x2, 400000 <_init-0x5f0>
  400788:	f946f842 	ldr	x2, [x2, #3568]
  40078c:	b4000042 	cbz	x2, 400794 <register_tm_clones+0x34>
  400790:	d61f0040 	br	x2
  400794:	d65f03c0 	ret

0000000000400798 <__do_global_dtors_aux>:
  400798:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40079c:	910003fd 	mov	x29, sp
  4007a0:	f9000bf3 	str	x19, [sp, #16]
  4007a4:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  4007a8:	39418260 	ldrb	w0, [x19, #96]
  4007ac:	35000080 	cbnz	w0, 4007bc <__do_global_dtors_aux+0x24>
  4007b0:	97ffffe0 	bl	400730 <deregister_tm_clones>
  4007b4:	52800020 	mov	w0, #0x1                   	// #1
  4007b8:	39018260 	strb	w0, [x19, #96]
  4007bc:	f9400bf3 	ldr	x19, [sp, #16]
  4007c0:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4007c4:	d65f03c0 	ret

00000000004007c8 <frame_dummy>:
  4007c8:	17ffffe6 	b	400760 <register_tm_clones>

00000000004007cc <init>:
  4007cc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007d0:	910003fd 	mov	x29, sp
  4007d4:	d2800300 	mov	x0, #0x18                  	// #24
  4007d8:	97ffff9a 	bl	400640 <malloc@plt>
  4007dc:	f9000fa0 	str	x0, [x29, #24]
  4007e0:	f9400fa0 	ldr	x0, [x29, #24]
  4007e4:	f100001f 	cmp	x0, #0x0
  4007e8:	540000c1 	b.ne	400800 <init+0x34>  // b.any
  4007ec:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  4007f0:	9137e000 	add	x0, x0, #0xdf8
  4007f4:	97ffffa3 	bl	400680 <puts@plt>
  4007f8:	12800000 	mov	w0, #0xffffffff            	// #-1
  4007fc:	97ffff8d 	bl	400630 <exit@plt>
  400800:	f9400fa0 	ldr	x0, [x29, #24]
  400804:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400808:	d65f03c0 	ret

000000000040080c <create>:
  40080c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400810:	910003fd 	mov	x29, sp
  400814:	f9000fa0 	str	x0, [x29, #24]
  400818:	f9400fa0 	ldr	x0, [x29, #24]
  40081c:	f9001fa0 	str	x0, [x29, #56]
  400820:	9100b3a1 	add	x1, x29, #0x2c
  400824:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400828:	91384000 	add	x0, x0, #0xe10
  40082c:	97ffff9d 	bl	4006a0 <__isoc99_scanf@plt>
  400830:	14000013 	b	40087c <create+0x70>
  400834:	d2800300 	mov	x0, #0x18                  	// #24
  400838:	97ffff82 	bl	400640 <malloc@plt>
  40083c:	f9001ba0 	str	x0, [x29, #48]
  400840:	f9401fa0 	ldr	x0, [x29, #56]
  400844:	f9401ba1 	ldr	x1, [x29, #48]
  400848:	f9000801 	str	x1, [x0, #16]
  40084c:	f9401ba0 	ldr	x0, [x29, #48]
  400850:	f9401fa1 	ldr	x1, [x29, #56]
  400854:	f9000401 	str	x1, [x0, #8]
  400858:	b9402fa1 	ldr	w1, [x29, #44]
  40085c:	f9401ba0 	ldr	x0, [x29, #48]
  400860:	b9000001 	str	w1, [x0]
  400864:	f9401ba0 	ldr	x0, [x29, #48]
  400868:	f9001fa0 	str	x0, [x29, #56]
  40086c:	9100b3a1 	add	x1, x29, #0x2c
  400870:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400874:	91384000 	add	x0, x0, #0xe10
  400878:	97ffff8a 	bl	4006a0 <__isoc99_scanf@plt>
  40087c:	b9402fa0 	ldr	w0, [x29, #44]
  400880:	7100001f 	cmp	w0, #0x0
  400884:	54fffd81 	b.ne	400834 <create+0x28>  // b.any
  400888:	f9400fa0 	ldr	x0, [x29, #24]
  40088c:	f9401fa1 	ldr	x1, [x29, #56]
  400890:	f9000401 	str	x1, [x0, #8]
  400894:	f9401fa0 	ldr	x0, [x29, #56]
  400898:	f9400fa1 	ldr	x1, [x29, #24]
  40089c:	f9000801 	str	x1, [x0, #16]
  4008a0:	f9400fa0 	ldr	x0, [x29, #24]
  4008a4:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4008a8:	d65f03c0 	ret

00000000004008ac <display>:
  4008ac:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4008b0:	910003fd 	mov	x29, sp
  4008b4:	f9000fa0 	str	x0, [x29, #24]
  4008b8:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  4008bc:	91386000 	add	x0, x0, #0xe18
  4008c0:	97ffff70 	bl	400680 <puts@plt>
  4008c4:	f9400fa0 	ldr	x0, [x29, #24]
  4008c8:	f90017a0 	str	x0, [x29, #40]
  4008cc:	f94017a0 	ldr	x0, [x29, #40]
  4008d0:	f9400800 	ldr	x0, [x0, #16]
  4008d4:	f90017a0 	str	x0, [x29, #40]
  4008d8:	f94017a0 	ldr	x0, [x29, #40]
  4008dc:	b9400001 	ldr	w1, [x0]
  4008e0:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  4008e4:	9138c000 	add	x0, x0, #0xe30
  4008e8:	97ffff72 	bl	4006b0 <printf@plt>
  4008ec:	f94017a0 	ldr	x0, [x29, #40]
  4008f0:	f9400800 	ldr	x0, [x0, #16]
  4008f4:	f90017a0 	str	x0, [x29, #40]
  4008f8:	f94017a1 	ldr	x1, [x29, #40]
  4008fc:	f9400fa0 	ldr	x0, [x29, #24]
  400900:	eb00003f 	cmp	x1, x0
  400904:	54fffea1 	b.ne	4008d8 <display+0x2c>  // b.any
  400908:	52800140 	mov	w0, #0xa                   	// #10
  40090c:	97ffff6d 	bl	4006c0 <putchar@plt>
  400910:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400914:	9138e000 	add	x0, x0, #0xe38
  400918:	97ffff5a 	bl	400680 <puts@plt>
  40091c:	f9400fa0 	ldr	x0, [x29, #24]
  400920:	f90017a0 	str	x0, [x29, #40]
  400924:	f94017a0 	ldr	x0, [x29, #40]
  400928:	f9400400 	ldr	x0, [x0, #8]
  40092c:	f90017a0 	str	x0, [x29, #40]
  400930:	f94017a0 	ldr	x0, [x29, #40]
  400934:	b9400001 	ldr	w1, [x0]
  400938:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  40093c:	9138c000 	add	x0, x0, #0xe30
  400940:	97ffff5c 	bl	4006b0 <printf@plt>
  400944:	f94017a0 	ldr	x0, [x29, #40]
  400948:	f9400400 	ldr	x0, [x0, #8]
  40094c:	f90017a0 	str	x0, [x29, #40]
  400950:	f94017a1 	ldr	x1, [x29, #40]
  400954:	f9400fa0 	ldr	x0, [x29, #24]
  400958:	eb00003f 	cmp	x1, x0
  40095c:	54fffea1 	b.ne	400930 <display+0x84>  // b.any
  400960:	52800140 	mov	w0, #0xa                   	// #10
  400964:	97ffff57 	bl	4006c0 <putchar@plt>
  400968:	d503201f 	nop
  40096c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400970:	d65f03c0 	ret

0000000000400974 <find>:
  400974:	d10083ff 	sub	sp, sp, #0x20
  400978:	f90007e0 	str	x0, [sp, #8]
  40097c:	b90007e1 	str	w1, [sp, #4]
  400980:	b90017ff 	str	wzr, [sp, #20]
  400984:	f94007e0 	ldr	x0, [sp, #8]
  400988:	f9000fe0 	str	x0, [sp, #24]
  40098c:	14000007 	b	4009a8 <find+0x34>
  400990:	f9400fe0 	ldr	x0, [sp, #24]
  400994:	f9400800 	ldr	x0, [x0, #16]
  400998:	f9000fe0 	str	x0, [sp, #24]
  40099c:	b94017e0 	ldr	w0, [sp, #20]
  4009a0:	11000400 	add	w0, w0, #0x1
  4009a4:	b90017e0 	str	w0, [sp, #20]
  4009a8:	f9400fe0 	ldr	x0, [sp, #24]
  4009ac:	f9400800 	ldr	x0, [x0, #16]
  4009b0:	f94007e1 	ldr	x1, [sp, #8]
  4009b4:	eb00003f 	cmp	x1, x0
  4009b8:	540000a0 	b.eq	4009cc <find+0x58>  // b.none
  4009bc:	b94017e1 	ldr	w1, [sp, #20]
  4009c0:	b94007e0 	ldr	w0, [sp, #4]
  4009c4:	6b00003f 	cmp	w1, w0
  4009c8:	54fffe4b 	b.lt	400990 <find+0x1c>  // b.tstop
  4009cc:	b94007e1 	ldr	w1, [sp, #4]
  4009d0:	b94017e0 	ldr	w0, [sp, #20]
  4009d4:	6b00003f 	cmp	w1, w0
  4009d8:	54000061 	b.ne	4009e4 <find+0x70>  // b.any
  4009dc:	f9400fe0 	ldr	x0, [sp, #24]
  4009e0:	14000002 	b	4009e8 <find+0x74>
  4009e4:	d2800000 	mov	x0, #0x0                   	// #0
  4009e8:	910083ff 	add	sp, sp, #0x20
  4009ec:	d65f03c0 	ret

00000000004009f0 <location>:
  4009f0:	d10083ff 	sub	sp, sp, #0x20
  4009f4:	f90007e0 	str	x0, [sp, #8]
  4009f8:	b90007e1 	str	w1, [sp, #4]
  4009fc:	b90017ff 	str	wzr, [sp, #20]
  400a00:	f94007e0 	ldr	x0, [sp, #8]
  400a04:	f9000fe0 	str	x0, [sp, #24]
  400a08:	14000007 	b	400a24 <location+0x34>
  400a0c:	f9400fe0 	ldr	x0, [sp, #24]
  400a10:	f9400800 	ldr	x0, [x0, #16]
  400a14:	f9000fe0 	str	x0, [sp, #24]
  400a18:	b94017e0 	ldr	w0, [sp, #20]
  400a1c:	11000400 	add	w0, w0, #0x1
  400a20:	b90017e0 	str	w0, [sp, #20]
  400a24:	f9400fe0 	ldr	x0, [sp, #24]
  400a28:	f9400800 	ldr	x0, [x0, #16]
  400a2c:	f94007e1 	ldr	x1, [sp, #8]
  400a30:	eb00003f 	cmp	x1, x0
  400a34:	540000c0 	b.eq	400a4c <location+0x5c>  // b.none
  400a38:	f9400fe0 	ldr	x0, [sp, #24]
  400a3c:	b9400000 	ldr	w0, [x0]
  400a40:	b94007e1 	ldr	w1, [sp, #4]
  400a44:	6b00003f 	cmp	w1, w0
  400a48:	54fffe21 	b.ne	400a0c <location+0x1c>  // b.any
  400a4c:	f9400fe0 	ldr	x0, [sp, #24]
  400a50:	b9400000 	ldr	w0, [x0]
  400a54:	b94007e1 	ldr	w1, [sp, #4]
  400a58:	6b00003f 	cmp	w1, w0
  400a5c:	54000061 	b.ne	400a68 <location+0x78>  // b.any
  400a60:	b94017e0 	ldr	w0, [sp, #20]
  400a64:	14000002 	b	400a6c <location+0x7c>
  400a68:	52800000 	mov	w0, #0x0                   	// #0
  400a6c:	910083ff 	add	sp, sp, #0x20
  400a70:	d65f03c0 	ret

0000000000400a74 <insert>:
  400a74:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a78:	910003fd 	mov	x29, sp
  400a7c:	f9000fa0 	str	x0, [x29, #24]
  400a80:	b90017a1 	str	w1, [x29, #20]
  400a84:	b90013a2 	str	w2, [x29, #16]
  400a88:	b94017a0 	ldr	w0, [x29, #20]
  400a8c:	51000400 	sub	w0, w0, #0x1
  400a90:	2a0003e1 	mov	w1, w0
  400a94:	f9400fa0 	ldr	x0, [x29, #24]
  400a98:	97ffffb7 	bl	400974 <find>
  400a9c:	f90017a0 	str	x0, [x29, #40]
  400aa0:	f94017a0 	ldr	x0, [x29, #40]
  400aa4:	f100001f 	cmp	x0, #0x0
  400aa8:	540000c1 	b.ne	400ac0 <insert+0x4c>  // b.any
  400aac:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400ab0:	91394000 	add	x0, x0, #0xe50
  400ab4:	97fffef3 	bl	400680 <puts@plt>
  400ab8:	d2800000 	mov	x0, #0x0                   	// #0
  400abc:	14000016 	b	400b14 <insert+0xa0>
  400ac0:	d2800300 	mov	x0, #0x18                  	// #24
  400ac4:	97fffedf 	bl	400640 <malloc@plt>
  400ac8:	f90013a0 	str	x0, [x29, #32]
  400acc:	f94013a0 	ldr	x0, [x29, #32]
  400ad0:	b94013a1 	ldr	w1, [x29, #16]
  400ad4:	b9000001 	str	w1, [x0]
  400ad8:	f94013a0 	ldr	x0, [x29, #32]
  400adc:	f94017a1 	ldr	x1, [x29, #40]
  400ae0:	f9000401 	str	x1, [x0, #8]
  400ae4:	f94017a0 	ldr	x0, [x29, #40]
  400ae8:	f9400801 	ldr	x1, [x0, #16]
  400aec:	f94013a0 	ldr	x0, [x29, #32]
  400af0:	f9000801 	str	x1, [x0, #16]
  400af4:	f94017a0 	ldr	x0, [x29, #40]
  400af8:	f9400800 	ldr	x0, [x0, #16]
  400afc:	f94013a1 	ldr	x1, [x29, #32]
  400b00:	f9000401 	str	x1, [x0, #8]
  400b04:	f94017a0 	ldr	x0, [x29, #40]
  400b08:	f94013a1 	ldr	x1, [x29, #32]
  400b0c:	f9000801 	str	x1, [x0, #16]
  400b10:	f9400fa0 	ldr	x0, [x29, #24]
  400b14:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400b18:	d65f03c0 	ret

0000000000400b1c <delete>:
  400b1c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400b20:	910003fd 	mov	x29, sp
  400b24:	f9000fa0 	str	x0, [x29, #24]
  400b28:	b90017a1 	str	w1, [x29, #20]
  400b2c:	b94017a1 	ldr	w1, [x29, #20]
  400b30:	f9400fa0 	ldr	x0, [x29, #24]
  400b34:	97ffff90 	bl	400974 <find>
  400b38:	f90017a0 	str	x0, [x29, #40]
  400b3c:	f94017a0 	ldr	x0, [x29, #40]
  400b40:	f100001f 	cmp	x0, #0x0
  400b44:	54000260 	b.eq	400b90 <delete+0x74>  // b.none
  400b48:	f94017a0 	ldr	x0, [x29, #40]
  400b4c:	f9400800 	ldr	x0, [x0, #16]
  400b50:	f100001f 	cmp	x0, #0x0
  400b54:	540001e0 	b.eq	400b90 <delete+0x74>  // b.none
  400b58:	f94017a0 	ldr	x0, [x29, #40]
  400b5c:	f9400400 	ldr	x0, [x0, #8]
  400b60:	f94017a1 	ldr	x1, [x29, #40]
  400b64:	f9400821 	ldr	x1, [x1, #16]
  400b68:	f9000801 	str	x1, [x0, #16]
  400b6c:	f94017a0 	ldr	x0, [x29, #40]
  400b70:	f9400800 	ldr	x0, [x0, #16]
  400b74:	f94017a1 	ldr	x1, [x29, #40]
  400b78:	f9400421 	ldr	x1, [x1, #8]
  400b7c:	f9000401 	str	x1, [x0, #8]
  400b80:	f94017a0 	ldr	x0, [x29, #40]
  400b84:	97fffec3 	bl	400690 <free@plt>
  400b88:	f9400fa0 	ldr	x0, [x29, #24]
  400b8c:	14000002 	b	400b94 <delete+0x78>
  400b90:	d2800000 	mov	x0, #0x0                   	// #0
  400b94:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400b98:	d65f03c0 	ret

0000000000400b9c <length>:
  400b9c:	d10083ff 	sub	sp, sp, #0x20
  400ba0:	f90007e0 	str	x0, [sp, #8]
  400ba4:	b90017ff 	str	wzr, [sp, #20]
  400ba8:	f94007e0 	ldr	x0, [sp, #8]
  400bac:	f9000fe0 	str	x0, [sp, #24]
  400bb0:	14000007 	b	400bcc <length+0x30>
  400bb4:	f9400fe0 	ldr	x0, [sp, #24]
  400bb8:	f9400800 	ldr	x0, [x0, #16]
  400bbc:	f9000fe0 	str	x0, [sp, #24]
  400bc0:	b94017e0 	ldr	w0, [sp, #20]
  400bc4:	11000400 	add	w0, w0, #0x1
  400bc8:	b90017e0 	str	w0, [sp, #20]
  400bcc:	f9400fe0 	ldr	x0, [sp, #24]
  400bd0:	f9400800 	ldr	x0, [x0, #16]
  400bd4:	f94007e1 	ldr	x1, [sp, #8]
  400bd8:	eb00003f 	cmp	x1, x0
  400bdc:	54fffec1 	b.ne	400bb4 <length+0x18>  // b.any
  400be0:	b94017e0 	ldr	w0, [sp, #20]
  400be4:	910083ff 	add	sp, sp, #0x20
  400be8:	d65f03c0 	ret

0000000000400bec <main>:
  400bec:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400bf0:	910003fd 	mov	x29, sp
  400bf4:	97fffef6 	bl	4007cc <init>
  400bf8:	f90017a0 	str	x0, [x29, #40]
  400bfc:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c00:	9139c000 	add	x0, x0, #0xe70
  400c04:	97fffe9f 	bl	400680 <puts@plt>
  400c08:	f94017a0 	ldr	x0, [x29, #40]
  400c0c:	97ffff00 	bl	40080c <create>
  400c10:	f90017a0 	str	x0, [x29, #40]
  400c14:	f94017a0 	ldr	x0, [x29, #40]
  400c18:	97ffff25 	bl	4008ac <display>
  400c1c:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c20:	913a4000 	add	x0, x0, #0xe90
  400c24:	97fffe97 	bl	400680 <puts@plt>
  400c28:	910063a1 	add	x1, x29, #0x18
  400c2c:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c30:	91384000 	add	x0, x0, #0xe10
  400c34:	97fffe9b 	bl	4006a0 <__isoc99_scanf@plt>
  400c38:	b9401ba0 	ldr	w0, [x29, #24]
  400c3c:	2a0003e1 	mov	w1, w0
  400c40:	f94017a0 	ldr	x0, [x29, #40]
  400c44:	97ffff4c 	bl	400974 <find>
  400c48:	f90013a0 	str	x0, [x29, #32]
  400c4c:	b9401ba1 	ldr	w1, [x29, #24]
  400c50:	f94013a0 	ldr	x0, [x29, #32]
  400c54:	b9400002 	ldr	w2, [x0]
  400c58:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c5c:	913aa000 	add	x0, x0, #0xea8
  400c60:	97fffe94 	bl	4006b0 <printf@plt>
  400c64:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c68:	913b2000 	add	x0, x0, #0xec8
  400c6c:	97fffe91 	bl	4006b0 <printf@plt>
  400c70:	910073a1 	add	x1, x29, #0x1c
  400c74:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c78:	91384000 	add	x0, x0, #0xe10
  400c7c:	97fffe89 	bl	4006a0 <__isoc99_scanf@plt>
  400c80:	b9401fa0 	ldr	w0, [x29, #28]
  400c84:	2a0003e1 	mov	w1, w0
  400c88:	f94017a0 	ldr	x0, [x29, #40]
  400c8c:	97ffff59 	bl	4009f0 <location>
  400c90:	b9001ba0 	str	w0, [x29, #24]
  400c94:	b9401ba1 	ldr	w1, [x29, #24]
  400c98:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400c9c:	913b8000 	add	x0, x0, #0xee0
  400ca0:	97fffe84 	bl	4006b0 <printf@plt>
  400ca4:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400ca8:	913c0000 	add	x0, x0, #0xf00
  400cac:	97fffe81 	bl	4006b0 <printf@plt>
  400cb0:	910073a2 	add	x2, x29, #0x1c
  400cb4:	910063a1 	add	x1, x29, #0x18
  400cb8:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400cbc:	913ca000 	add	x0, x0, #0xf28
  400cc0:	97fffe78 	bl	4006a0 <__isoc99_scanf@plt>
  400cc4:	b9401ba0 	ldr	w0, [x29, #24]
  400cc8:	b9401fa1 	ldr	w1, [x29, #28]
  400ccc:	2a0103e2 	mov	w2, w1
  400cd0:	2a0003e1 	mov	w1, w0
  400cd4:	f94017a0 	ldr	x0, [x29, #40]
  400cd8:	97ffff67 	bl	400a74 <insert>
  400cdc:	f90017a0 	str	x0, [x29, #40]
  400ce0:	f94017a0 	ldr	x0, [x29, #40]
  400ce4:	97fffef2 	bl	4008ac <display>
  400ce8:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400cec:	913cc000 	add	x0, x0, #0xf30
  400cf0:	97fffe70 	bl	4006b0 <printf@plt>
  400cf4:	910073a1 	add	x1, x29, #0x1c
  400cf8:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400cfc:	91384000 	add	x0, x0, #0xe10
  400d00:	97fffe68 	bl	4006a0 <__isoc99_scanf@plt>
  400d04:	b9401fa0 	ldr	w0, [x29, #28]
  400d08:	2a0003e1 	mov	w1, w0
  400d0c:	f94017a0 	ldr	x0, [x29, #40]
  400d10:	97ffff83 	bl	400b1c <delete>
  400d14:	f90017a0 	str	x0, [x29, #40]
  400d18:	f94017a0 	ldr	x0, [x29, #40]
  400d1c:	97fffee4 	bl	4008ac <display>
  400d20:	f94017a0 	ldr	x0, [x29, #40]
  400d24:	97ffff9e 	bl	400b9c <length>
  400d28:	b9001ba0 	str	w0, [x29, #24]
  400d2c:	b9401ba1 	ldr	w1, [x29, #24]
  400d30:	90000000 	adrp	x0, 400000 <_init-0x5f0>
  400d34:	913d2000 	add	x0, x0, #0xf48
  400d38:	97fffe5e 	bl	4006b0 <printf@plt>
  400d3c:	52800000 	mov	w0, #0x0                   	// #0
  400d40:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d44:	d65f03c0 	ret

0000000000400d48 <__libc_csu_init>:
  400d48:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d4c:	910003fd 	mov	x29, sp
  400d50:	a901d7f4 	stp	x20, x21, [sp, #24]
  400d54:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10084>
  400d58:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10084>
  400d5c:	91374294 	add	x20, x20, #0xdd0
  400d60:	913722b5 	add	x21, x21, #0xdc8
  400d64:	a902dff6 	stp	x22, x23, [sp, #40]
  400d68:	cb150294 	sub	x20, x20, x21
  400d6c:	f9001ff8 	str	x24, [sp, #56]
  400d70:	2a0003f6 	mov	w22, w0
  400d74:	aa0103f7 	mov	x23, x1
  400d78:	9343fe94 	asr	x20, x20, #3
  400d7c:	aa0203f8 	mov	x24, x2
  400d80:	97fffe1c 	bl	4005f0 <_init>
  400d84:	b4000194 	cbz	x20, 400db4 <__libc_csu_init+0x6c>
  400d88:	f9000bb3 	str	x19, [x29, #16]
  400d8c:	d2800013 	mov	x19, #0x0                   	// #0
  400d90:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400d94:	aa1803e2 	mov	x2, x24
  400d98:	aa1703e1 	mov	x1, x23
  400d9c:	2a1603e0 	mov	w0, w22
  400da0:	91000673 	add	x19, x19, #0x1
  400da4:	d63f0060 	blr	x3
  400da8:	eb13029f 	cmp	x20, x19
  400dac:	54ffff21 	b.ne	400d90 <__libc_csu_init+0x48>  // b.any
  400db0:	f9400bb3 	ldr	x19, [x29, #16]
  400db4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400db8:	a942dff6 	ldp	x22, x23, [sp, #40]
  400dbc:	f9401ff8 	ldr	x24, [sp, #56]
  400dc0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400dc4:	d65f03c0 	ret

0000000000400dc8 <__libc_csu_fini>:
  400dc8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400dcc <_fini>:
  400dcc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400dd0:	910003fd 	mov	x29, sp
  400dd4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400dd8:	d65f03c0 	ret
